This invention relates to integrated circuits (ICs), and more particularly to a decoupling capacitor structure for use with fine-pitched Ball Grid Array (BGA) packaged ICs.
Integrated circuits (ICs) require a power supply voltage that is connected to a power supply lead of the IC through a power supply interconnection (e.g., a conductive trace formed on a printed circuit board (PCB) hosting both the IC and the power supply). This power supply interconnection can be a source of emitted or received electromagnetic interference (EMI). For example, EMI can be emitted through the power supply interconnection in response to high frequency electronic signals operating within the IC. Similarly, externally generated EMI can be received through the power supply interconnection, which acts as an antenna, that can affect the operation of the electronic circuitry within the IC.
The amount of EMI generated in a power supply interconnection is generally dependent upon the physical distance between the power supply lead of the IC and a decoupling capacitor electrically connected to the power supply lead. Therefore, EMI can be reduced by minimizing the length of the power supply interconnection between the decoupling capacitor and the power supply lead of the IC.
FIG. 1 is a perspective view showing a conventional chip capacitor 100, which is representative of a class of low-cost decoupling capacitors used to minimize EMI in electronic systems. Chip capacitors are well-known surface mount device constructed according to subsection 8.2 of the Surface Mount Design and Land Pattern Standard published by the Institute for Interconnecting and Packaging Electronic Circuits (IPC-SM-782, May 1996, Revision A). Chip capacitor 100 includes a box-shaped housing 110, and has a first terminal 112 and a second terminal 114 located at opposite ends of housing 110. Terminals 112 and 114 are constructed to facilitate soldering to lands 122 and 124 that are provided, for example, on a PCB 210. Lands 122 and 124 are also specified in subsection 8.2 of the Surface Mount Design and Land Pattern Standard (cited above), and are typically connected by conductive traces to corresponding metal vias 211-1 and 211 (FIG. 2(A)) formed on PCB 210 according to known techniques.
FIGS. 2(A) and 2(B) are bottom plan and side cross-sectional views showing an assembly 200 in which a ball-grid array (BGA) packaged IC 220 is mounted on PCB 210 (partially shown in FIG. 1), and includes several conventional chip capacitors 100 that are provided to minimize EMI. BGA IC 220 includes an array of solder balls 221 that extend from a lower surface of a package substrate 222 and are soldered to corresponding contact pads formed on metal vias 211. Mounted on package substrate 222 is an IC chip 224 that is electrically connected to solder balls 221, and is protected by a cover (e.g., a xe2x80x9cglob topxe2x80x9d) 226. PCB 210 includes an array of metal vias 211 whose pitch (i.e., distance between adjacent vias) is determined by the corresponding pitch of solder balls 221 on BGA IC 220.
Referring to FIG. 2(A), when metal vias 211 are arranged close together to accommodate the fine pitch of solder balls 221, chip capacitors 100 must be arranged around the periphery P of the metal via array. As mentioned above, each chip capacitor requires a pair of lands (e.g., lands 122 and 124, which are shown in FIG. 1) of a specified size, and there is insufficient space between metal vias 211 to form these lands. Accordingly, chip capacitors 100 must be located outside of periphery P, which can result in increased EMI when one or more power supply leads are soldered to metal vias located in central region C of the metal via array. This is particularly true when two or more rows of chip capacitors 100 must be formed around periphery P.
Several conventional solutions are possible to address the problem of locating one or more chip capacitors in central region C of the metal via array shown in FIG. 2(A). First, the arrangement of solder balls 221 and/or metal vias 211 can be changed to provide the necessary space. However, this solution requires a costly re-design of standard BGA packages and/or the non-use of one or more leads on IC 220. Another solution may be to redesign the chip capacitor to fit within the narrow spaces provided between metal vias. Again, this solution requires an expensive redesign of the chip capacitor housing, which would greatly increase the cost of the chip capacitors.
What is needed is a capacitor structure that can be used as a decoupling capacitor and avoids the space requirement problems associated with convention chip capacitors (discussed above). Further, what is needed is a capacitor structure that has the low per-piece cost of conventional chip capacitors.
The present invention is directed to a BGA-type capacitor structure including a conventional chip capacitor mounted on the upper surface of an inexpensive substrate (e.g., polyimide tape), and having solder balls mounted on a lower surface of the substrate. Lands that are required to mount the chip capacitor are formed on the substrate, which is offset from the surface of a PCB by the solder balls. Accordingly, the capacitor structures of the present invention are easily integrated into a metal via array, thereby minimizing the spacing between the chip capacitor mounted thereon and a power supply lead of an integrated circuit also mounted on the PCB. Further, the size of the substrate is easily changed to accommodate a wide range of metal via pitches, thereby allowing the use of inexpensive conventional chip capacitors and avoiding costly redesigns.
In one embodiment of the present invention, the substrate is a thin sheet of polyimide tape that is etched or perforated to provide holes through which the solder balls contact the lands used to mount the chip capacitors.
The present invention is also directed to an assembly including a PCB having an array of metal vias extending between opposing upper and lower surfaces, a BGA IC mounted on the upper surface and soldered to first ends of the metal vias, and one or more capacitor structures soldered to contact pads formed on the lower surface of the PCB. Each capacitor structure includes the features described above. Each of the contact pads is connected by a conductive trace to the second ends of one or more associated metal vias, thereby minimizing the distance between the chip capacitor mounted on the capacitor structure and power supply leads formed on the BGA IC.